wafer.space Community - High voltage (10V) in gf180

6:46 a.m.

Thanks @Leo Moser (mole99) for your reply. It would be helpful if can get confirmation or any limitations wrt use of 10V devices from pdk in designs. Are IO pads available for supporting high voltage.

No . All io pads have esd diodes that wouldn't handle that.

7:27 a.m.

You will need to design your own AFAICT

So, existing pads support only upto 5V/6V; for 10V need to design custom IO pads. Is that correct ?

That's what it looks like to me yes.

@Vipul any particular plans for them? I'd like to help validate in preparation for X. I'd be looking forward to designing X some time next year. I'd expect usage of ldmos for local voltage regulation, perhaps in a mode of modulating whether or not a capacitive transformer/divider siphoning off the local power switch's drain voltage cycling gets to top off a local storage capacitor (off of which it would run an LDO or maybe even buck to provide 3.3V core and 5V output gate drive supply) or is just shorted out for the upcoming turn-off-transient; it'd have to also provide diode-action off the ldmos drain potential (as anode) to the local buffer capacitor (of which it'd e.g. LDO the 5V output gate drive "PA" and the 3.3V core supply; as cathode) especially during startup/power-on-reset. Probably; though it may end up using a separate supply regulating switch for that (EPC2106 perhaps, if there's a way to make a floating 5V CMOS output that can be ground-lifted those 5~10V). X: the isolated digital-predistortion-enabled gate driver for GaN (e.g. EPC2207) switched-capacitor converters (operating at considerably higher system voltages through operating the switches in series with very careful control as they're not said to be avalanche-proof (exceeding the drain-source breakdown voltage with gate-source voltage being the recommended off-state 0V would typically result in physical damage, AFAIK), by using fiber optics to provide isolation against sharp dV/dT for a central brain to coordinate a fleet of the drivers, each with a couple switching dies local to it that are in parallel and sufficiently monitored).

@namibj What I understand from your requirements is that you plan to design some kind of gate driver circuit for driving a GaN based switch. Please correct me if I am wrong. I don’t have much knowledge about GaN electronics, but do see potential applications of 10V ldmos in some types of battery management designs. Would be glad to explore this further, provided it’s feasible in gf180.

Vipul

@namibj What I understand from your requirements is that you plan to design some kind of gate driver circuit for driving a GaN based switch. Please correct me if I am wrong. I don’t have much knowledge about GaN electronics, but do see potential applications of 10V ldmos in some types of battery management designs. Would be glad to explore this further, provided it’s feasible in gf180.

No yeah that's about it. The complication comes from it not doing it the classic hard switched CMOS output stage way but rather with a class B output "PA" stage (technically an "independently" driven push/pull pair aka half-bridge is what drives the GaN gate, probably via a bit of impedance matching to recycle a decent chunk of the gate charge) fed from a pair of DACs that control the push and pull output driver individually as those will have limited speed and it's trying to reduce overall losses while staying coordinated across multiple GaN that are wired in series for more blocking voltage (if they do any hard switching it has to be synchronized or one catches excess voltage and blows discharge damage in it's channel! At least AFAIK these GaN are not avalanche-proof.). All the GaN you'd need to know to understand is just this "n-channel logic level mosfet" datasheet; I'd probably aim to use 120~150 normally and up to 180 non-repetitive (in fault containment) of the 200 V drain voltage. Note the total gate charge, gate-source charge, gate-drain charge, gate resistance, (if needed compute equivalent total gate-source capacitance from assuming total gate charge goes just to the source and then using the 5V gate-source voltage to turn the charge into a capacitance; for an RC time constant), and look how fast that 23(typ) 35 (max) nC output charge (@100V) charges from e.g. say 20A that should be feasible from the limited 25~35% effective duty cycle in the switching topologies I'm eyeing. https://epc-co.com/epc/portals/0/epc/documents/datasheets/EPC2207_datasheet.pdf E.g. about 2.3ns until drain full, 900 pF charge-equivalent input capacitance, 270ps RC time constant of the gate based off of that charge-equivalent capacitance and the gate resistance, 5+-0.5V gate-on target, 0V(+-0.5 if needed) (clamped) gate-off target, etc.

2:41 p.m.

I can explain differently later if needed/wanted.